1. Field of the Invention
This invention relates in general to jitter attenuators, and in particular, to a jitter attenuator circuit comprising a first order loop having a digital phase detector and a digital frequency synthesizer.
2. Description of Related Art
Jitter attenuation circuits are well known in the art for absorbing phase variations from signals. If these phase variations are not eliminated, they can cause significant errors in digital signals.
Improvements in jitter attenuators have been devised. One example of a prior jitter attenuator is shown in U.S. Pat. No. 5,162,746, issued Nov. 10, 1992, to Sajol Ghoshal (the same inventor as the present application), assigned to the Assignee of the present invention, and entitled "DIGITALLY CONTROLLED CRYSTAL-BASED JITTER ATTENUATOR," which patent is incorporated by reference herein. The '746 patent discloses a circuit for attenuating phase jitter on an incoming clock signal, which circuit includes a digitally controlled oscillator and a phase lock loop including a phase detector. The oscillator is capable of generating a plurality of discrete frequencies selectable through digitally controlled inputs controlling switched, capacitively-loaded amplifier stages. The phase detector consists primarily of an up/down counter with an overflow/underflow limiter circuit.
The oscillator in the '746 patent exhibits inadequate rejection behavior and jitter enhancement when the frequency of the incoming jittered clock is substantially the same as one of the frequencies selectable by the amplifier load capacitance, and thus requires a dithering circuit. In addition, the number of selectable frequencies is proportional to the number of component amplifiers in the oscillator circuit, and thus may result in designs requiring a large number of components. Further, the range of frequencies available from the oscillator are limited by the selection of capacitor, amplifier and crystal components. Finally, the oscillator has non-linearities in its jitter performance due to load variations as capacitors are added and removed, and the resulting jolt on the oscillator.
A different oscillator design can be found in U.S. Pat. No. 5,059,924, issued Oct. 22, 1991, to William S. Jennings Check, assigned to the Assignee of the present invention, and entitled "CLOCK ADAPTOR USING A PHASE LOCKED LOOP CONFIGURED AS A FREQUENCY MULTIPLIER WITH A NON-INTEGER FEEDBACK DIVIDER," which patent is incorporated by reference herein. The '924 patent discloses a phase locked loop configured as a frequency multiplier capable of non-integral feedback path division, which utilizes a multi-phase voltage controlled oscillator which generates a plurality of signals having a substantially identical frequency but each offset equally from the other by a given phase angle. A commutator selects signals of adjacent phases so as to give the time average output signal a higher or lower frequency. Frequency translation is accomplished by periodically selecting signals having a longer or shorter period as desired so that a commutator output signal is delayed or advanced by an appropriate amount.
The oscillator in the '924 patent eliminates the non-linearities of oscillator circuit in the '726 patent. Further, the oscillator makes predictable adjustments to its clock period based on specific requests. Moreover, the oscillator can make finer adjustments in its clock period to maintain low intrinsic jitter. Finally, it is capable of generating N discrete frequencies.
Thus, there is a need in the art for a Jitter attenuator circuit combining and improving on the best elements of the '924 and '746 patents.